This application claims priority and benefit of Korean Patent Application No. 10-2004-0091883, filed on Nov. 11, 2004, the disclosure of which is herein incorporated by reference in its entirety.
1. Field of the Invention
The invention relates to semiconductor memory devices, and more particularly, to a semiconductor device capable of storing data of various patterns and a method of electrically testing the same.
2. Description of the Related Art
Functions of semiconductor memory devices are electrically tested using address pins, data pins, and control pins included in the semiconductor memory devices. Testing the semiconductor memory devices simultaneously provides an efficient means of performing the electrical test and, thus, minimizes costs. However, since a tester has a limited number of channels, the number of semiconductor memory devices capable of being simultaneously tested, that is, being subject to a parallel test, is limited.
A means of increasing the number of semiconductor memory devices that can be simultaneously tested is by reducing the number of I/O channels of a tester allotted to data pins of semiconductor memory devices. A related technique was disclosed by Samsung Electronics Ltd in U.S. Pat. No. 6,323,664, issued to Kim, et al. on Nov. 27, 2001, entitled “Semiconductor Memory Device Capable of Accurately Testing for Defective Memory Cells at a Wafer Level.”
FIG. 1 is a block diagram of a memory cell array in a conventional test mode of a semiconductor memory device. FIG. 2 is a flowchart illustrating a method of electrically testing the semiconductor memory device of FIG. 1.
Referring to FIGS. 1 and 2, the semiconductor memory device includes data input/output pads PAD0 through PAD31 and a memory cell array 18, to and from which data can be written and read.
To undergo an electrical function test, the semiconductor memory device is connected to a tester 16 via a probe card/device under test (DUT) board 14. To reduce the number of I/O channels 10 of the tester 16 used to test the semiconductor memory device, the data input/output pads PAD0 through PAD31 are divided into groups MDQ0 through MDQ7, each of which include four data input/output pads. One representative data input/output pad from each group is the coupled to one I/O channel 10 of the tester 16 via an assigned probe needle 12 of the probe card/DUT board 14. For example, PAD0 is selected as the representative data input/output pad of the group MDQ0 and PAD4 is selected as the representative data input/output pad of the group MDQ1. Thus, eight representative data input/output pads PAD0, PAD4, . . . , PAD28 are coupled to the tester 16 via probe needles 12 of the probe card/DUT board 14.
In an electrical test of a semiconductor memory device based on the design scheme shown in FIG. 1, a general direct current (DC) test and a function test for memory devices are performed first. As shown in FIG. 2, to test a writing function of the memory cell array 18, the I/O channels 10 of the tester 16 via the probe card/DUT board 14 send to-be-written data to memory cells through the representative pads PAD0, PAD4, . . . , PAD28. The data is transferred not only to data input buffers DIN_BUF0, DIN_BUF4, . . . , DIN_BUF28 corresponding to the representative pads PAD0, PAD4, . . . , PAD28, but also to the remaining data input buffers via a data transfer path for a test mode illustrated by a dotted line in FIG. 1, and written to the memory cell array 18, in operation S10. Then, the written data is read out from the memory cell array 18 to check if the memory cell array 18 is normal or defective, in operation S20.
In the conventional art as shown in FIG. 1, when data is written to the memory cell array 18 via representative pads PAD0, PAD4, . . . , and PAD28 of groups MDQ0 through MDQ7, identical data bits are transmitted to the four input/output pads in each group. For example, a data bit of 0 or 1 is transferred to all of the four input/output pads PAD0, PAD1, PAD2, and PAD3 in group MDQ0. Thus, when different data bits are written through neighboring input/output pads, it is impossible to determine defective memory cells. For example, when data of 1111 is written to neighboring memory cells of the memory cell array 18 through input/output pads in a group, for example, PAD0 through PAD3 of group MDQ0, the writing test is properly performed. However, when data of 1010 is written to neighboring memory cells of the memory cell array 18, defective cells cannot be checked.
As described above, in the conventional art, semiconductor devices can be effectively parallel tested by reducing the number of I/O channels of a tester that are assigned to data pins of the semiconductor devices. However, in the conventional art, accurately testing the memory cell array 18 through writing of data of various bit patterns is limited.